I have completed my B.E. (Electronics and Communication Engineering) and M.E. (Embedded Systems) from Anna University, Tamilnadu in 2009 and 2011 respectively. I obtained a Ph.D. degree from Indian Institute of Information Technology Design and Manufacturing (IIITDM) Kancheepuram, India in July 2016. My Ph.D. work mainly focuses on VLSI architectures for various discrete transformations such as DWT, FFT, DHT, and integer DCT. Also, it includes the basic signal processing elements such as MAC, multi-precision multiplier, an efficient high fan-in multiplexer. Currently, I work as a Post Doctoral Fellow in the department of Computer Science and Engineering, Indian Institute of Technology (IIT) Kanpur, India, where my research deals with asynchronous crypto hardware implementations, Galois arithmetic, Bloom filter based payload matching, decision tree/TCAM based packet classification, backplane switch interconnects, and hardware-software co-designs using Artix-7 FPGA with Xilinx and Cadence ASIC design tool (Genus and Innovus). My research interest includes VLSI architectures for cryptography, signal processing, network packet processing elements, and reconfigurable designs.